Search - cpu design vhdl

[Books] MCUDesign

Description: 《Digital Logic And Microprocessor Design With VHDL》，CPU设计经典参考书-"Digital Logic And Microprocessor Design With VHDL, "CPU design classic reference books
Platform: | Size: 4815872 | Author: hanberg | Hits:

[VHDL-FPGA-Verilog] cpuTerminate

Description: 用VHDL 编写的一个16位的cpu 设计方案，可以执行8条指令。-use VHDL to prepare a 16 cpu design of the program, the implementation of eight instructions.
Platform: | Size: 2108416 | Author: 宋文强 | Hits:

[VHDL-FPGA-Verilog] vhdl_8cpu

Description: VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
Platform: | Size: 52224 | Author: 紫蓝 | Hits:

[Other] VHDL-FPGA-clock

Description: ＦＰＧＡ数字钟的设计，用VHDL语言编程，max+plus仿真，可在实际电路中验证-FPGA design, VHDL programming, max plus simulation, in the actual circuit verification
Platform: | Size: 269312 | Author: 王越 | Hits:

[VHDL-FPGA-Verilog] the-design-of-16-bit-cpu

Description: 用vhdl硬件语言设计的16位cpu，上传的压缩包既包含源代码又包含详细的文档说明。-with vhdl hardware design language of the 16 cpu, Upload compressed contains both the source code also contains a detailed document shows.
Platform: | Size: 128000 | Author: 晶晶 | Hits:

[Other] SAP-1Cpu

Description: EDA的课程设计，自己写到PPT，大致讲了用VHDL语言实现简易CPU的设计，有源码-EDA s curriculum design, wrote their own PPT, generally speaking the use of VHDL language simple CPU design, with source
Platform: | Size: 278528 | Author: gaoliang | Hits:

[Other] cpu

Description: 初学cpu设计（完全教程）包括verilog代码以及文档说明那个-Beginner cpu design (complete tutorial) includes a Verilog code as well as the document explains that
Platform: | Size: 366592 | Author: hjx | Hits:

[VHDL-FPGA-Verilog] controlunit

Description: CPU设计中的controlunit源码，其中附带了时序仿真。通过Sequencing Logic 产生 control_signals,具体的信号可在controlsignal.mif文件中直接修改。 -CPU design controlunit source, which comes with timing simulation. Sequencing Logic generated through control_signals, specific signals can directly modify the controlsignal.mif document.
Platform: | Size: 328704 | Author: ck | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[VHDL-FPGA-Verilog] MyCPU16

Description: 16位cpu设计VHDL源码，其中包括alu，clock，memory等部分的设计-16 cpu design VHDL source code, including alu, clock, memory and other parts of the design
Platform: | Size: 1089536 | Author: 孙冰 | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[VHDL-FPGA-Verilog] lab80

Description: 基于FPGA的CPU设计 VHDL 编写-FPGA-CPU design based on VHDL prepared
Platform: | Size: 3051520 | Author: 鹏鹏 | Hits:

[VHDL-FPGA-Verilog] 8-cpu

Description: 8位CPU的VHDL设计,16条指令系统,以及部分测试代码,开发工具是quartusii_60_pc-8-bit CPU of the VHDL design, 16 instruction, as well as some of the test code, development tools is quartusii_60_pc
Platform: | Size: 3072 | Author: FJ | Hits:

[VHDL-FPGA-Verilog] RiscCPU8

Description: 可综合的VerilogHDL设计实例: ---简化的RISC 8位CPU设计简介--- -VerilogHDL be integrated design example:--- simplified RISC 8 bit CPU design Introduction---
Platform: | Size: 219136 | Author: hulin | Hits:

[File Format] modelcomputer

Description: 基于模型机的设计，进行简单的CPU设计并实现基本的指令，如加、减、转移等。-Model-based design, a simple CPU design and realization of the basic commands, such as add, subtract, transfer.
Platform: | Size: 287744 | Author: 刘金玲 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: cpu的vhdl设计实现加法减法乘法运算-cpu VHDL Design and Implementation of multiplication addition subtraction
Platform: | Size: 2012160 | Author: 郭红 | Hits:

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

Description: MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
Platform: | Size: 918528 | Author: 李皓 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[ARM-PowerPC-ColdFire-MIPS] CPU

Description: 简单的CPU设计,使用VHDL 和 quartus ii 设计的cpu(a simply cpu design, vhdl quartus ii ,dsg gs h srh rsh rsh srjh srh)
Platform: | Size: 1488896 | Author: fgsdgsdg | Hits:

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[Books] MCUDesign

[VHDL-FPGA-Verilog] cpuTerminate

[VHDL-FPGA-Verilog] vhdl_8cpu

[Other] VHDL-FPGA-clock

[VHDL-FPGA-Verilog] the-design-of-16-bit-cpu

[Other] SAP-1Cpu

[Other] cpu

[VHDL-FPGA-Verilog] controlunit

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] MyCPU16

[VHDL-FPGA-Verilog] LC3-VHDL-another

[VHDL-FPGA-Verilog] lab80

[VHDL-FPGA-Verilog] 8-cpu

[VHDL-FPGA-Verilog] RiscCPU8

[File Format] modelcomputer

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] cpu

[ARM-PowerPC-ColdFire-MIPS] CPU

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